1. Field of the Invention
The present invention relates generally to logic circuits, and more particularly to high speed CMOS circuit configurations for use with pulsed active inputs.
2. Background
Advances in semiconductor manufacturing technologies have allowed circuit designers to integrate tremendous numbers of transistors on a single die. For example, modern integrated circuits (ICs) commonly include several million transistors interconnected on a single, small substrate. Typically these are field effect transistors (FET). At the same time, computer architecture, and more particularly processor architecture, has gone in the direction of emphasizing shorter and shorter cycle times. These advances in semiconductor manufacturing and processor architecture have led designers to consider new ways of implementing basic circuit functions.
To produce IC's with shorter cycle times typically requires increasing the clock frequency at which these devices operate. Increasing clock frequencies means that fewer logic gate delays are permitted within each clock cycle. Yet modern processor acrchitecture typically requires a significant amount of logical operations to take place as quickly as possible. As described below, several styles of logic design have been developed to achieve high speed operation.
Static full CMOS logic requires one p-channel field effect transistor (PFET) for each n-channel field effect transistor (NFET). For complex logic gates this means either an NFET stack with a PFET OR structure, or an NFET OR structure with a PFET stack. FIG. 1(a) shows the transistor level configuration of a static full CMOS complex logic gate. FIG. 1(b) shows a logic symbol representing the logical function implemented by the circuit of FIG. 1(a). The physical layout of these complex logic gate structures produces a substantial amount junction area, and thus parasitic capacitance, associated with the output node.
Dynamic logic structures, e.g., domino logic, have been developed which reduce the amount of parasitic capacitance at the output node relative to static full CMOS logic structures. Domino logic refers to a circuit arrangement in which there are several series coupled logic stages having precharged output nodes. An aggregation of several series coupled domino logic stages is referred to as a domino block. Alternatively, the domino block is referred to as a pipestage, since it is often used to implement pipelined architectures in high speed CMOS logic integrated circuits. The output node of an individual logic stage is precharged to a first logic level, logic signals are then applied such that, depending on the logic function being implemented and the state of the various input signals, the output node can be switched to a second logic level. As each domino stage in the chain evaluates, the output of the next domino stage may be enabled to switch. Since the precharged nodes "fall" in sequence, the operation has been analogized to falling dominoes, and hence the name for this type of circuit arrangement.
While domino circuits do tend to reduce both input capacitance and output capacitance as compared to static full CMOS logic structures, domino circuits require reset (i.e., precharge) circuitry, and further domino circuits are sensitive to charge sharing induced noise problems.
What is needed is a structure that provides high speed combinatorial logic functions, consumes a small amount of chip area, presents less input and output capacitance than static full CMOS logic structures, and is insensitive to charge sharing problems.